(1) Field of the Invention
The present invention relates to a method and device for controlling a CPU stop clock interrupt. More particularly, the present invention controls a stop clock interrupt of a Static Low-Power Central Processing Unit (hereinafter referred to as SL CPU), such as that manufactured by Intel Corporation, with the use of an idle detector and a control processor.
(2) Description of the Related Art
Computer systems with power-saving functions are well known. Such computer systems enable users to switch the computer from a normal operating mode to a power-off mode, which reduces power consumption if there is no user input for a predetermined period of time, and to switch it back into a resume-mode if there is any input requiring the system to resume normal operations.
An SL CPU such as that manufactured by Intel provides modes, which if selected, can greatly reduce power consumption. Accordingly, it is ideally suited for use in computer systems having power-saving functions.
For example, an SL CPU provides a stop clock interrupt terminal for allowing external control of system clock speed. Conventionally, a system controller chipset, such as that which is further illustrated in the following description, is employed to externally control the clock speed of the SL CPU through the stop clock interrupt terminal.
A conventional stop clock interrupt controller will be described with reference to the FIG. 1 block diagram of a conventional stop clock interrupt controller.
As shown in FIG. 1, the conventional stop clock interrupt controller comprises a system controller chipset 5 (shown as SCC in the drawing), which is very expensive, and SL CPU 4, of which a stop clock interrupt terminal STPCLK is connected with an output terminal of the system controller chipset 5. Operation of the conventional stop clock interrupt controller is described below.
To reduce power consumption during specific operating modes, the system controller chipset 5 is especially designed to generate a stop clock interrupt signal to control the clock speed of the SL CPU 4. When the system controller chipset 5 outputs the stop clock interrupt signal to the SL CPU 4, the SL CPU 4 conserves power by lowering its clock speed.
However, as described above, the conventional stop clock interrupt controller requires a very expensive system controller chipset 5. Therefore, the cost of producing a computer system including a conventional power-saving feature is increased by the cost of conventionally providing that feature.
Furthermore, because the conventional stop clock controller generates a stop clock interrupt only in the specific modes for which it is designed to do so, a user can not voluntarily control the clock speed of the SL CPU 4 for any other purpose through the stop clock interrupt terminal STPCLK of SL CPU 4. Likewise, once an interrupt is generated, a slow clock mode is entered, but resuming a normal mode of the SL CPU 4 can only be implemented in a restricted number of ways since a conventional stop clock interrupt controller is also required to clear the clock interrupt mode.